1. Field of the Invention
The present invention relates to a method for manufacturing a high-voltage semiconductor device. More particularly, the present invention relates to an ion implantation method for forming a high-voltage device.
2. Discussion of the Related Art
Generally, semiconductor devices which are capable of operating at high voltages include a high-voltage transistor capable of operating in a high-voltage environment, and a second low-voltage transistor constituting a logic circuit.
A high-voltage transistor requires a resistance against a high voltage, and has a structure with high breakdown voltage and voltage/current control characteristics. Examples of high-voltage transistor structures include double-diffusion structures, lateral-diffusion structures, expanded drain structures, and the like. By way of comparison, the second low-voltage transistor constituting a logic circuit requires rapid operational characteristics including high-integration properties and low-electricity requirements. Typically, the low-voltage transistor has a hollow junction structure which exhibits superior short channel effects and hot carrier characteristics.
The low-voltage transistor of the logic circuit and the high-voltage transistor have different gate insulation thicknesses. Generally, the gate insulation layer in a logic region has a thickness of approximately 20 Å, while the gate insulation layer in the high-voltage region has a thickness of approximately 140 Å. Because of the different thicknesses in the gate insulation layers in the low-voltage and high-voltage transistors, it is difficult to form a transistor junction in the high-voltage region using the ion implantation process used for forming a transistor junction in the logic circuit. Thus, there is a need for separate masking processes in order to form the junction of the logic circuit and the junction in the high-voltage region.
Because the photolithography processes used a semiconductor manufacturing method are very costly and time-consuming, it is necessary to reduce the number of the processes in order to enhance productivity. Thus, forming an impurity diffusion layer in both the logic region and the high-voltage region using separate ion implantation processes, which have the same conductivity and density conditions using different ion implantation masks results in enormous losses in both time and cost. For this reason, there is an urgent need for a method of a simplified manufacturing process which overcomes the previously described problem.